(i) Technical Field
The present invention relates to semiconductor devices, and more particularly, to a semiconductor device having a substrate having a via hole.
(i) Related Art
A via hole may be formed in a substrate on which a semiconductor element such as an FET (Field Effect Transistor) is formed so as to communicate with the front surface of the substrate and the back surface thereof. The inner surface of the via hole is coated with a metal layer, and an electric connection with a semiconductor element may be made via the via hole from the back surface of the substrate. It is thus possible to reduce the parasitic impedance in the electric connection with the semiconductor element.
Japanese Patent Application Publication No. 2000-138236 discloses a substrate having a via hole having an elliptic shape.
However, a crack may be generated in the substrate with the via hole by stress applied to the substrate due to a temperature cycle or a warpage of a mounting board on which the substrate is mounted. An increased size of via hole attempted to suppress the crack generated in the substrate increases the chip area.